{\scriptsize
\begin{lstlisting}
% ============================
% OBJECTS
% ============================

time(0).

% ============================
% CIRCUIT STRUCTURE
% ============================

wire(1..6).
gate(1..3).
and(1).
inverter(2).
or(3).

% and gate has inputs 1 and 2

input_to(1,1..2).

% inverter has input 3

input_to(2,3).

% or gate has inputs 4 and 5

input_to(3,4..5).

% and gate has output 4

output_from(1,4).

% inverter has output 5

output_from(2,5).

% or gate has output 6

output_from(3,6).

% ============================
% GENERAL DESCRIPTION OF GATES
% ============================

h(val(OUTPUT_WIRE, 1), T) :- 
    output_from(GATE, OUTPUT_WIRE),
    and(GATE),
    input_to(GATE, INPUT1),
    input_to(GATE, INPUT2),
    INPUT1 != INPUT2,
    h(val(INPUT1, 1), T),
    h(val(INPUT2, 1), T),
    time(T).

h(val(OUTPUT_WIRE, 0), T) :- 
    output_from(GATE, OUTPUT_WIRE),
    and(GATE),
    input_to(GATE, INPUT),
    h(val(INPUT, 0), T),
    time(T).
    
h(val(OUTPUT_WIRE, 0), T) :- 
    output_from(GATE, OUTPUT_WIRE),
    or(GATE),
    input_to(GATE, INPUT1),
    input_to(GATE, INPUT2),
    INPUT1 != INPUT2,
    h(val(INPUT1, 0), T),
    h(val(INPUT2, 0), T),
    time(T).

h(val(OUTPUT_WIRE, 1), T) :- 
    output_from(GATE, OUTPUT_WIRE),
    or(GATE),
    input_to(GATE, INPUT),
    h(val(INPUT, 1), T),
    time(T).
    
h(val(OUTPUT_WIRE, 1), T) :-
    output_from(GATE, OUTPUT_WIRE),
    inverter(GATE),
    input_to(GATE, INPUT),
    h(val(INPUT, 0), T),
    time(T).

h(val(OUTPUT_WIRE, 0), T) :-
    output_from(GATE, OUTPUT_WIRE),
    inverter(GATE),
    input_to(GATE, INPUT),
    h(val(INPUT, 1), T),
    time(T).

% ============================
% INITIAL STATE
% ============================
    
h(val(1, 1), 0).
h(val(2, 0), 0).
h(val(3, 1), 0).

% ============================
% SOLVER DIRECTIVES
% ============================

#hide.
#show h(_,_).
\end{lstlisting}
}